vishay siliconix dg787 document number: 65369 s09-1936-rev. b, 28-sep-09 www.vishay.com 1 300-mhz, 2.5- , dual spdt analog switches features ? 1.8 v to 5.5 v operation ?2.5 at 2.7 v r on ? 300 mhz - 3 db bandwidth ? esd per mil-std-883 method 3015.7 > 2 kv ? latch-up current 200 ma (jesd 78) ? 1.6 v logic compatible ? compliant to rohs directive 2002/95/ec ? halogen-free according to iec 61249-2-21 definition benefits ? space saving msop-10 package ? high linearity ? low power consumption ? high bandwidth ? full rail signal swing range applications ? cellular phones ?mp3 ? media players ? modems ? hard drives ? pcmcia description the dg787 are dual spdt analog switches which operate from 1.8 v to 5.5 v single rail power supply. they are design for audio, video, and usb switching applications. the devices have 2.5 on-resistance and 300 mhz 3 db bandwidth. 0.2 on-resistance matching and 1 flatness make the device high linearity. the devices are 1.6 v logic compatible within the full operation voltage range. these switches are built on a sub-micron high density process that brings low power consumption and low voltage performance. the switch is package in msop 10 package. as a committed partner to the community and the environment, vishay siliconix manufactures this product with lead (pb)-free device terminations. dg787 is offered in a msop package. the msop package uses 100 % matte tin device termination and is represented by the lead (pb)-free ?-e3? suffix. both the matte tin device terminations meet all jedec standards for reflow and msl ratings. functional block diagram and pin configuration v+ dg787 top view 1 2 3 4 5 no 1 com 1 in 1 nc 1 no 2 10 9 8 7 6 com 2 in 2 nc 2 gnd truth table logic nc1 and nc2 no1 and no2 0 on off 1offon ordering information temp. range package part number - 40 c to 85 c msop-10 dG787DQ-T1-E3
www.vishay.com 2 document number: 65369 s09-1936-rev. b, 28-sep-09 vishay siliconix dg787 notes: a. signals on nc, no, or com or in exceeding v+ will be clamped by inte rnal diodes. limit forward diode current to maximum curr ent ratings. b. refer to ipc/jedec (j-std-020). c. all leads welded or soldered to pc board. d. derate 4.0 mw/c above 70 c. stresses beyond those listed under ?absolute maximum ratings? ma y cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other condit ions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings parameter limit unit reference v+ to gnd - 0.3 to + 6 v in, com, nc, no a - 0.3 to (v+ + 0.3) continuous current (no, nc, com) 100 ma peak current (pulsed at 1 ms, 10 % duty cycle) 500 storage temperature (d suffix) - 65 to 150 c esd per mil-std-883 method 3015.7 > 2 kv power dissipation (packages) c msop-10 d 320 mw specifications v+ = 3 v parameter symbol test conditions otherwise unless specified v+ = 2.7 v to 3.6 v, v in = 0.5 v or 1.4 v e temp. a limits - 40 c to 85 c unit min. b typ. c max. b analog switch analog signal range d v no , v nc , v com full 0 v+ v on-resistance d r on v+ = 2.7 v i no , i nc = 10 ma v com = 1.5 v room full 2.5 3.5 3.8 r on flatness d r on flatness v com = 1, 1.5, 2 v room 0.52 1.0 on-resistance match between channels d r ds(on) v com = 1.5 v room 0.25 switch off leakage current i no(off) i nc(off) v+ = 3.3 v, v no , v nc = 0.3 v/3 v, v com = 3 v/0.3 v room full - 1 - 20 1 20 na i com(off) room full - 1 - 20 1 20 channel-on leakage current i com(on) v+ = 3.3 v, v no , v nc = v com = 0.3 v/3 v room full - 1 - 20 1 20 digital control input high voltage d v inh full 1.4 v input low voltage v inl full 0.5 input capacitance c in full 5 pf input current i inl or i inh v in = 0 or v+ full 1 1 a
document number: 65369 s09-1936-rev. b, 28-sep-09 www.vishay.com 3 vishay siliconix dg787 specifications v+ = 3 v parameter symbol test conditions otherwise unless specified v+ = 2.7 v to 3.6 v, v in = 0.5 v or 1.4 v e temp. a limits - 40 c to 85 c unit min. b typ. c max. b dynamic characteristics tu r n - o n t i m e t on v+ = 2.7 v, v no or v nc = 1.5 v r l = 300 , c l = 35 pf room full 21 51 52 ns turn-off time t off room full 15 45 46 break-before-make time t d full 1 charge injection d q inj c l = 1 nf, v gen = 2.0 v, r gen = 0 room 1 pc off-isolation d oirr r l = 50 , c l = 5 pf f = 1 mhz room - 74 db f = 10 mhz room - 54 crosstalk d x ta l k f = 1 mhz room - 76 f = 10 mhz room - 56 n o , n c off capacitance d c no(off) v in = 0 or v+, f = 1 mhz room 12 pf c nc(off) room 12 channel-on capacitance d c no(on) room 40 c nc(on) room 40 power supply power supply current i+ v in = 0 or v+ room full 1.0 1.0 a
www.vishay.com 4 document number: 65369 s09-1936-rev. b, 28-sep-09 vishay siliconix dg787 notes: a. room = 25 c, full = as determined by the operating suffix. b. typical values are for design aid only, not guaranteed nor subject to production testing. c. the algebraic convention whereby the most negative value is a minimum and the most po sitive a maximum, is used in this datas heet. d. guarantee by design, nor s ubjected to production test. e. v in = input voltage to perform proper function. f. guaranteed by 5 v testing, not production tested. specifications v+ = 5 v parameter symbol test conditions otherwise unless specified v+ = 4.2 v to 5.5 v, v in = 0.8 v or 2.0 v e temp. a limits - 40 c to 85 c unit min. b typ. c max. b analog switch analog signal range d v no , v nc , v com full 0 v+ v on-resistance d r on v+ = 4.2 v i no , i nc = 10 ma v com = 3.5 v room full 2.2 2.9 3.1 r on flatness d r on flatness v com = 1, 2, 3.5 v room 0.53 1.0 on-resistance match between channels d r ds(on) v com = 3.5 v room 0.25 switch off leakage current i no(off) i nc(off) v+ = 5.5 v, v no , v nc = 1 v/4.5 v, v com = 4.5 v/1 v room full - 1 - 20 1 20 na i com(off) room full - 1 - 20 1 20 channel-on leakage current i com(on) v+ = 5.5 v, v no , v nc = v com = 1 v/4.5 v room full - 1 - 20 1 20 digital control input high voltage d v inh full 2.0 v input low voltage v inl full 0.8 input capacitance c in full 5 pf input current i inl or i inh v in = 0 or v+ full 1 1 a dynamic characteristics tu r n - o n t i m e t on v+ = 4.2 v, v no or v nc = 3.0 v r l = 300 , c l = 35 pf room full 15 45 46 ns turn-off time t off room full 12 42 43 break-before-make time t d full 1 charge injection d q inj c l = 1 nf, v gen = 2.0 v, r gen = 0 room 1 pc off-isolation d oirr r l = 50 , c l = 5 pf f = 1 mhz room - 74 db f = 10 mhz room - 54 crosstalk d x ta l k f = 1 mhz room - 78 f = 10 mhz room - 56 n o , n c off capacitance d c no(off) v in = 0 or v+, f = 1 mhz room 12 pf c nc(off) room 12 channel-on capacitance d c no(on) room 40 c nc(on) room 40 power supply power supply current i+ v in = 0 or v+ room full 1.0 1.0 a
document number: 65369 s09-1936-rev. b, 28-sep-09 www.vishay.com 5 vishay siliconix dg787 typical characteristics 25 c, unless otherwise noted r on vs. v com and single supply voltage 0 1 2 3 4 5 6 7 8 012345 v com - analog voltage (v) t = 25 c i s = 10 ma - on-resistance ( ) r on v+ = 1.8 v v+ = 2.0 v v+ = 2.7 v v+ = 3.0 v v+ = 3.6 v v+ = 4.2 v v+ = 5.0 v v+ = 5.5 v r on vs. analog voltage and temperature supply current vs. temperature 0 1 2 3 4 5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 v com - analog voltage (v) - on-resistance ( ) r on v+ = 2.7 v i s = 10 ma 85 c 25 c - 40 c - 60 - 40 - 20 0 20 40 60 80 100 10 10 000 100 000 temperature (c) 100 1000 i+ - supply current (na) v+ = 3.0 v v in = 0 v r on vs. analog voltage and temperature supply current vs. input switching frequency 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 012345 v com - analog voltage (v) - on-resistance ( ) r on v+ = 4.2 v i s = 10 ma 85 c 25 c - 40 c 10 10k 100k 10m 100 1k 1m 100 ma 10 ma 1 ma 100 a 10 a 1 a 100 na 1 na input switching frequency (hz) i+ - supply current (a) v+ = 3.0 v 10 na
www.vishay.com 6 document number: 65369 s09-1936-rev. b, 28-sep-09 vishay siliconix dg787 typical characteristics 25 c, unless otherwise noted leakage current vs. temperature switching time vs. temperature switching threshold vs. supply voltage - 60 - 40 - 20 0 20 40 60 80 100 1 10 000 temperature (c) v+ = 3.0 v 100 1000 leakage current (pa) i com(on) i no(off) , i nc(off) 10 i com(off) 0 5 10 15 20 25 - 60 - 40 - 20 0 20 40 60 80 100 / t on - switching t ime (ns) t off t off v+ = 4.2 v temperature (c) t on v+ = 2.7 v t off v+ = 2.7 v t on v+ = 4.2 v 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 0123456 v+ - supply voltage (v) - switching threshold (v) v t leakage vs. analog voltage insertion loss, off-isolation crosstalk vs. frequency charge injection vs. analog voltage - 800 - 600 - 400 - 200 0 200 400 600 800 0.0 0.6 1.2 1.8 2.4 3.0 3.6 v com , v no , v nc - analog voltage (v) leakage current (pa) v+ = 3.6 v i com(on) i com(off) i no(off) , i nc(off) 100k - 90 10m 10 - 70 - 50 100m 1g 1m frequency (hz) (db) loss, oirr, x talk - 30 - 10 oirr x talk v+ = 3.0 v r l loss - 10 - 8 - 6 - 4 - 2 0 2 4 6 8 10 012345 v com - analog voltage (v) q - charge injection (pc) v+ = 3.0 v v+ = 2.0 v v+ = 5.0 v
document number: 65369 s09-1936-rev. b, 28-sep-09 www.vishay.com 7 vishay siliconix dg787 test circuits figure 1. switching time switch input c l (includes fixture and stray capacitance) v+ in no or nc c l 35 pf com logic input r l 300 v out gnd v+ 50 % 0 v logic input switch output t on t off logic ?1? = switch on logic input waveforms inverted for switches that have the opposite logic sense. 0 v switch output v out =v com ( r l r l +r on ) 0.9 x v out t r < 5 ns t f < 5 ns v inh v inl figure 2. break-before-make interval c l (includes fixture and stray capacitance) nc v no no v nc 0 v logic input switch output v o v nc = v no 90 % t d in com v+ gnd v+ c l 35 pf v o r l 300 v inl v inh t r < 5 ns t f < 5 ns t d figure 3. charge injection c l = 1 nf r gen v out com v in = 0 - v+ in gnd v+ v+ + nc or no off on on in v out v out q = v out x c l in depends on switch configuration: input polarity determined by sense of switch.
www.vishay.com 8 document number: 65369 s09-1936-rev. b, 28-sep-09 vishay siliconix dg787 test circuits vishay siliconix maintains worldwide manufacturing capability. products may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?65369 . figure 4. off-isolation in gnd nc or no 0 v, 2.4 v 10 nf com off isolation = 20 log v com v no / nc r l analyzer v+ v+ com figure 5. channel off/on capacitance nc or no f = 1 mhz in com gnd 0 v, 2.4 v meter hp4192a impedance analyzer or equivalent 10 nf v+ v+
notes: 1. die thickness allowable is 0.203 0.0127. 2. dimensioning and tolerances per ansi.y14.5m-1994. 3. dimensions ?d? and ?e 1 ? do not include mold flash or protrusions, and are measured at datum plane -h- , mold flash or protrusions shall not exceed 0.15 mm per side. 4. dimension is the length of terminal for soldering to a substrate. 5. terminal positions are shown for reference only. 6. formed leads shall be planar with respect to one another within 0.10 mm at seating plane. 7. the lead width dimension does not include dambar protrusion. allowable dambar protrusion shall be 0.08 mm total in excess of the lead width dimension at maximum material condition. dambar cannot be located on the lower radius or the lead foot. minimum space between protrusions and an adjacent lead to be 0.14 mm. see detail ?b? and section ?c-c?. 8. section ?c-c? to be determined at 0.10 mm to 0.25 mm from the lead tip. 9. controlling dimension: millimeters. 10. this part is compliant with jedec registration mo-187, variation aa and ba. 11. datums -a- and -b- to be determined datum plane -h- . 12. exposed pad area in bottom side is the same as teh leadframe pad size. 5 n n-1 a b c 0.20 (n/2) tips) 2x n/2 2 1 0.60 0.50 0.60 e top view e see detail ?b? -h- 3 d -a- seating plane a 1 a 6 c 0.10 side view 0.25 bsc 4 l -c- seating plane 0.07 r. min 2 places parting line detail ?a? (scale: 30/1) 0.48 max detail ?b? (scale: 30/1) dambar protrusion 7 c 0.08 m b s a s b b 1 with plating base metal c 1 c section ?c-c? scale: 100/1 (see note 8) see detail ?a? a 2 0.05 s c c ? 3 e 1 -b- end view e1 0.95 package information vishay siliconix document number: 71245 12-jul-02 www.vishay.com 1 msop: 10?leads jedec part number: mo-187, (variation aa and ba) n = 10l millimeters dim min nom max note a - - 1.10 a 1 0.05 0.10 0.15 a 2 0.75 0.85 0.95 b 0.17 - 0.27 8 b 1 0.17 0.20 0.23 8 c 0.13 - 0.23 c 1 0.13 0.15 0.18 d 3.00 bsc 3 e 4.90 bsc e 1 2.90 3.00 3.10 3 e 0.50 bsc e 1 2.00 bsc l 0.40 0.55 0.70 4 n 10 5 0 4 6 ecn: t-02080?rev. c, 15-jul-02 dwg: 5867
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